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<title>Streaming SIMD Extensions</title>

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<span id="openzim-page-title" class="mw-page-title-main"><span class="mw-page-title-main">Streaming SIMD Extensions</span></span>

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<p>In <a href="Computing" title="Computing">computing</a>, <b>Streaming SIMD Extensions</b> (<b>SSE</b>) is a single instruction, multiple data (<a href="SIMD" class="mw-redirect" title="SIMD">SIMD</a>) <a href="Instruction_set" class="mw-redirect" title="Instruction set">instruction set</a> extension to the <a href="X86" title="X86">x86</a> architecture, designed by <a href="Intel" title="Intel">Intel</a> and introduced in 1999 in its <a href="Pentium_III" title="Pentium III">Pentium III</a> series of <a href="Central_processing_unit" title="Central processing unit">central processing units</a> (CPUs) shortly after the appearance of <a href="Advanced_Micro_Devices" class="mw-redirect" title="Advanced Micro Devices">Advanced Micro Devices</a> (AMD's) <a href="3DNow!" title="3DNow!">3DNow!</a>. SSE contains 70 new instructions (65 unique mnemonics<sup id="cite_ref-1" class="reference"><a href="#cite_note-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup> using 70 encodings), most of which work on <a href="Single_precision" class="mw-redirect" title="Single precision">single precision</a> <a href="Floating-point" class="mw-redirect" title="Floating-point">floating-point</a> data. SIMD instructions can greatly increase performance when exactly the same operations are to be performed on multiple data objects. Typical applications are <a href="Digital_signal_processing" title="Digital signal processing">digital signal processing</a> and <a href="Graphics_processing" class="mw-redirect" title="Graphics processing">graphics processing</a>.

</p><p>Intel's first <a href="IA-32" title="IA-32">IA-32</a> SIMD effort was the <a href="MMX_(instruction_set)" title="MMX (instruction set)">MMX</a> instruction set. MMX had two main problems: it re-used existing <a href="X87" title="X87">x87</a> floating-point registers making the CPUs unable to work on both floating-point and SIMD data at the same time, and it only worked on <a href="Integers" class="mw-redirect" title="Integers">integers</a>. SSE floating-point instructions operate on a new independent register set, the XMM registers, and adds a few integer instructions that work on MMX registers.

</p><p>SSE was subsequently expanded by Intel to <a href="SSE2" title="SSE2">SSE2</a>, <a href="SSE3" title="SSE3">SSE3</a>, <a href="SSSE3" title="SSSE3">SSSE3</a> and <a href="SSE4" title="SSE4">SSE4</a>. Because it supports floating-point math, it had wider applications than MMX and became more popular. The addition of integer support in SSE2 made MMX largely redundant, though further performance increases can be attained in some situations by using MMX in parallel with SSE operations.

</p><p>SSE was originally called <b>Katmai New Instructions</b> (<b>KNI</b>), <a href="Katmai_(microprocessor)" class="mw-redirect" title="Katmai (microprocessor)">Katmai</a> being the code name for the first Pentium III core revision. During the Katmai project Intel sought to distinguish it from its earlier product line, particularly its flagship <a href="Pentium_II" title="Pentium II">Pentium II</a>. It was later renamed <b>Internet Streaming SIMD Extensions</b> (<b>ISSE</b><sup id="cite_ref-MPR=1999-03-08_2-0" class="reference"><a href="#cite_note-MPR=1999-03-08-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup>), then SSE.

</p><p>AMD added a subset of SSE, 19 of them, called new MMX instructions,<sup id="cite_ref-extman_3-0" class="reference"><a href="#cite_note-extman-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup> and known as several variants and combinations of SSE and MMX, shortly after with the release of the original <a href="Athlon" title="Athlon">Athlon</a> in August 1999, see <a href="3DNow!#3DNow!_extensions" title="3DNow!">3DNow! extensions</a>. AMD eventually added full support for SSE instructions, starting with its <a href="Athlon_XP" class="mw-redirect" title="Athlon XP">Athlon XP</a> and <a href="Duron" title="Duron">Duron</a> (<a href="Duron#Morgan_(Model_7,_180_nm)" title="Duron">Morgan core</a>) processors.

</p>

<div class="mw-heading mw-heading2"><h2 id="Registers">Registers</h2></div>

<p>SSE originally added eight new 128-bit registers known as <code>XMM0</code> through <code>XMM7</code>. The <a href="AMD64" class="mw-redirect" title="AMD64">AMD64</a> extensions from AMD added a further eight registers <code>XMM8</code> through <code>XMM15</code>, and this extension is duplicated in the <a href="Intel_64" class="mw-redirect" title="Intel 64">Intel 64</a> architecture. There is also a new 32-bit control/status register, <code>MXCSR</code>. The registers <code>XMM8</code> through <code>XMM15</code> are accessible only in 64-bit operating mode.

</p>

<p>SSE used only a single data type for XMM registers:

</p>

<ul><li>four 32-bit <a href="Single-precision" class="mw-redirect" title="Single-precision">single-precision</a> floating-point numbers</li></ul>

<p><a href="SSE2" title="SSE2">SSE2</a> would later expand the usage of the XMM registers to include:

</p>

<ul><li>two 64-bit <a href="Double-precision" class="mw-redirect" title="Double-precision">double-precision</a> floating-point numbers or</li>

<li>two 64-bit integers or</li>

<li>four 32-bit integers or</li>

<li>eight 16-bit short integers or</li>

<li>sixteen 8-bit bytes or characters.</li></ul>

<p>Because these 128-bit registers are additional machine states that the <a href="Operating_system" title="Operating system">operating system</a> must preserve across <a href="Context_switch" title="Context switch">task switches</a>, they are disabled by default until the operating system explicitly enables them. This means that the OS must know how to use the <code>FXSAVE</code> and <code>FXRSTOR</code> instructions, which is the extended pair of instructions that can save all <a href="X86" title="X86">x86</a> and SSE register states at once. This support was quickly added to all major IA-32 operating systems.

</p><p>The first CPU to support SSE, the <a href="Pentium_III" title="Pentium III">Pentium III</a>, shared execution resources between SSE and the <a href="Floating-point_unit" title="Floating-point unit">floating-point unit</a> (FPU).<sup id="cite_ref-MPR=1999-03-08_2-1" class="reference"><a href="#cite_note-MPR=1999-03-08-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup> While a <a href="Compiled" class="mw-redirect" title="Compiled">compiled</a> application can interleave FPU and SSE instructions side-by-side, the Pentium III will not issue an FPU and an SSE instruction in the same <a href="Clock_cycle" class="mw-redirect" title="Clock cycle">clock cycle</a>. This limitation reduces the effectiveness of <a href="Instruction_pipeline" class="mw-redirect" title="Instruction pipeline">pipelining</a>, but the separate XMM registers do allow SIMD and scalar floating-point operations to be mixed without the performance hit from explicit MMX/floating-point mode switching.

</p>

<div class="mw-heading mw-heading2"><h2 id="SSE_instructions">SSE instructions</h2></div>

<p>SSE introduced both <a href="Scalar_(computing)" class="mw-redirect" title="Scalar (computing)">scalar</a> and <a href="Data_structure_alignment" title="Data structure alignment">packed</a> floating-point instructions.

</p>

<div class="mw-heading mw-heading3"><h3 id="Floating-point_instructions">Floating-point instructions</h3></div>

<p>Floating operations are IEEE 754-1985 compliant, with the exception of <code>RSQRTSS</code>, which is not specified in the standard.

</p>

<ul><li>Memory-to-register/register-to-memory/register-to-register data movement

<ul><li>Scalar – <code>MOVSS</code></li>

<li>Packed – <code>MOVAPS, MOVUPS, MOVLPS, MOVHPS, MOVLHPS, MOVHLPS, MOVMSKPS</code></li></ul></li>

<li>Arithmetic

<ul><li>Scalar – <code>ADDSS, SUBSS, MULSS, DIVSS, RCPSS, SQRTSS, MAXSS, MINSS, RSQRTSS</code></li>

<li>Packed – <code>ADDPS, SUBPS, MULPS, DIVPS, RCPPS, SQRTPS, MAXPS, MINPS, RSQRTPS</code></li></ul></li>

<li><a href="Comparison_(computer_programming)" class="mw-redirect" title="Comparison (computer programming)">Compare</a>

<ul><li>Scalar – <code>CMPSS, COMISS, UCOMISS</code></li>

<li>Packed – <code>CMPPS</code></li></ul></li>

<li>Data shuffle and unpacking

<ul><li>Packed – <code>SHUFPS, UNPCKHPS, UNPCKLPS</code></li></ul></li>

<li><a href="Type_conversion" title="Type conversion">Data-type conversion</a>

<ul><li>Scalar – <code>CVTSI2SS, CVTSS2SI, CVTTSS2SI</code></li>

<li>Packed – <code>CVTPI2PS, CVTPS2PI, CVTTPS2PI</code></li></ul></li>

<li><a href="Bitwise_operation" title="Bitwise operation">Bitwise</a> logical operations

<ul><li>Packed – <code>ANDPS, ORPS, XORPS, ANDNPS</code></li></ul></li></ul>

<div class="mw-heading mw-heading3"><h3 id="Integer_instructions">Integer instructions</h3></div>

<ul><li>Arithmetic

<ul><li><code>PMULHUW, PSADBW, PAVGB, PAVGW, PMAXUB, PMINUB, PMAXSW, PMINSW</code></li></ul></li>

<li>Data movement

<ul><li><code>PEXTRW, PINSRW</code></li></ul></li>

<li>Other

<ul><li><code>PMOVMSKB, PSHUFW</code></li></ul></li></ul>

<div class="mw-heading mw-heading3"><h3 id="Other_instructions">Other instructions</h3></div>

<ul><li><code>MXCSR</code> management

<ul><li><code>LDMXCSR, STMXCSR</code></li></ul></li>

<li>Cache and Memory management

<ul><li><code>MOVNTQ, MOVNTPS, MASKMOVQ, PREFETCH0, PREFETCH1, PREFETCH2, PREFETCHNTA, SFENCE</code></li></ul></li></ul>

<div class="mw-heading mw-heading2"><h2 id="Example">Example</h2></div>

<p>The following simple example demonstrates the advantage of using SSE. Consider an operation like vector addition, which is used very often in computer graphics applications. To add two single precision, four-component vectors together using x86 requires four floating-point addition instructions.

</p>

</pre></div>

<p>This corresponds to four x86 FADD instructions in the object code. On the other hand, as the following pseudo-code shows, a single 128-bit 'packed-add' instruction can replace the four scalar addition instructions.

</p>

<div class="mw-highlight mw-highlight-lang-nasm mw-content-ltr" dir="ltr"><pre><span class="w"> </span><span class="nf">movaps</span><span class="w"> </span><span class="nb">xmm0</span><span class="p">,</span><span class="w"> </span><span class="p">[</span><span class="nv">v1</span><span class="p">]</span><span class="w"> </span><span class="c1">;xmm0 = v1.w | v1.z | v1.y | v1.x </span>

<span class="w"> </span><span class="nf">addps</span><span class="w"> </span><span class="nb">xmm0</span><span class="p">,</span><span class="w"> </span><span class="p">[</span><span class="nv">v2</span><span class="p">]</span><span class="w"> </span><span class="c1">;xmm0 = v1.w+v2.w | v1.z+v2.z | v1.y+v2.y | v1.x+v2.x</span>

<span class="w"> </span><span class="nf">movaps</span><span class="w"> </span><span class="p">[</span><span class="nv">vec_res</span><span class="p">],</span><span class="w"> </span><span class="nb">xmm0</span><span class="w"> </span><span class="c1">;xmm0</span>

</pre></div>

<div class="mw-heading mw-heading2"><h2 id="Later_versions">Later versions</h2></div>

<ul><li><a href="SSE2" title="SSE2">SSE2</a>, Willamette New Instructions (WNI), introduced with the <a href="Pentium_4" title="Pentium 4">Pentium 4</a>, is a major enhancement to SSE. SSE2 adds two major features: <a href="Double-precision" class="mw-redirect" title="Double-precision">double-precision</a> (64-bit) floating-point for all SSE operations, and MMX integer operations on 128-bit XMM registers. In the original SSE instruction set, conversion to and from integers placed the integer data in the 64-bit MMX registers. SSE2 enables the programmer to perform SIMD math on any data type (from 8-bit integer to 64-bit float) entirely with the XMM vector-register file, without the need to use the legacy MMX or FPU registers. It offers an <a href="Orthogonal_instruction_set" title="Orthogonal instruction set">orthogonal set of instructions</a> for dealing with common data types.</li>

<li><a href="SSE3" title="SSE3">SSE3</a>, also called Prescott New Instructions (PNI), is an incremental upgrade to SSE2, adding a handful of DSP-oriented mathematics instructions and some process (thread) management instructions. It also allowed addition or multiplication of two numbers that are stored in the same register, which wasn't possible in SSE2 and earlier. This capability, known as horizontal in Intel terminology, was the major addition to the SSE3 instruction set. AMD's <a href="3DNow!" title="3DNow!">3DNow!</a> extension could do the latter too.</li>

<li><a href="SSSE3" title="SSSE3">SSSE3</a>, Merom New Instructions (MNI), is an upgrade to SSE3, adding 16 new instructions which include permuting the bytes in a word, multiplying 16-bit fixed-point numbers with correct rounding, and within-word accumulate instructions. SSSE3 is often mistaken for SSE4 as this term was used during the development of the Core <a href="Microarchitecture" title="Microarchitecture">microarchitecture</a>.</li>

<li><a href="SSE4" title="SSE4">SSE4</a>, Penryn New Instructions (PNI), is another major enhancement, adding a <a href="Dot_product" title="Dot product">dot product</a> instruction, additional integer instructions, a <a href="SSE4#POPCNT_and_LZCNT" title="SSE4"><code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" dir="ltr"><span class="nf">popcnt</span></code> instruction</a> (<a href="Hamming_weight" title="Hamming weight">Population count</a>: count number of bits set to 1, used extensively e.g. in <a href="Cryptography" title="Cryptography">cryptography</a>), and more.</li>

<li><a href="XOP_instruction_set" title="XOP instruction set">XOP</a>, <a href="FMA_instruction_set" title="FMA instruction set">FMA4</a> and <a href="CVT16_instruction_set" class="mw-redirect" title="CVT16 instruction set">CVT16</a> are new iterations announced by <a href="AMD" title="AMD">AMD</a> in August 2007<sup id="cite_ref-:0_4-0" class="reference"><a href="#cite_note-:0-4"><span class="cite-bracket">[</span>4<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-5" class="reference"><a href="#cite_note-5"><span class="cite-bracket">[</span>5<span class="cite-bracket">]</span></a></sup> and revised in May 2009.<sup id="cite_ref-6" class="reference"><a href="#cite_note-6"><span class="cite-bracket">[</span>6<span class="cite-bracket">]</span></a></sup></li>

<li><a href="Advanced_Vector_Extensions" title="Advanced Vector Extensions">Advanced Vector Extensions</a> (AVX), Gesher New Instructions (GNI), is an advanced version of SSE announced by Intel featuring a widened data path from 128 bits to 256 bits and 3-operand instructions (up from 2). Intel released processors in early 2011 with AVX support.<sup id="cite_ref-7" class="reference"><a href="#cite_note-7"><span class="cite-bracket">[</span>7<span class="cite-bracket">]</span></a></sup></li>

<li><a href="Advanced_Vector_Extensions#Advanced_Vector_Extensions_2" title="Advanced Vector Extensions">AVX2</a> is an expansion of the AVX instruction set.</li>

<li><a href="AVX-512" title="AVX-512">AVX-512</a> (3.1 and 3.2) are 512-bit extensions to the 256-bit Advanced Vector Extensions SIMD instructions for x86 instruction set architecture.</li></ul>

<div class="mw-heading mw-heading2"><h2 id="Identifying">Identifying</h2></div>

<p>The following programs can be used to determine which, if any, versions of SSE are supported on a system

</p>

<ul><li>Intel Processor Identification Utility<sup id="cite_ref-8" class="reference"><a href="#cite_note-8"><span class="cite-bracket">[</span>8<span class="cite-bracket">]</span></a></sup></li>

<li><a href="CPU-Z" title="CPU-Z">CPU-Z</a> – CPU, motherboard, and memory identification utility.</li>

<li><a href="Util-linux" title="Util-linux">lscpu</a> - provided by the util-linux package in most Linux distributions.</li></ul>

<ul><li><a href="AltiVec" title="AltiVec">AltiVec</a> - equivalent on <a href="PowerPC" title="PowerPC">PowerPC</a> architecture</li></ul>

<div class="mw-heading mw-heading2"><h2 id="References">References</h2></div>

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.mw-parser-output .reflist{margin-bottom:0.5em;list-style-type:decimal}@media screen{.mw-parser-output .reflist{font-size:90%}}.mw-parser-output .reflist .references{font-size:100%;margin-bottom:0;list-style-type:inherit}.mw-parser-output .reflist-columns-2{column-width:30em}.mw-parser-output .reflist-columns-3{column-width:25em}.mw-parser-output .reflist-columns{margin-top:0.3em}.mw-parser-output .reflist-columns ol{margin-top:0}.mw-parser-output .reflist-columns li{page-break-inside:avoid;break-inside:avoid-column}.mw-parser-output .reflist-upper-alpha{list-style-type:upper-alpha}.mw-parser-output .reflist-upper-roman{list-style-type:upper-roman}.mw-parser-output .reflist-lower-alpha{list-style-type:lower-alpha}.mw-parser-output .reflist-lower-greek{list-style-type:lower-greek}.mw-parser-output .reflist-lower-roman{list-style-type:lower-roman}

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</style><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://cdrdv2.intel.com/v1/dl/getContent/671200">"Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 1: Basic Architecture"</a>. Intel. April 2022. pp. 5-16–5-19. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20220425144301/https://cdrdv2.intel.com/v1/dl/getContent/671200">Archived</a> from the original on April 25, 2022<span class="reference-accessdate">. Retrieved <span class="nowrap">May 16,</span> 2022</span>.</cite></span>

</li>

<li id="cite_note-MPR=1999-03-08-2"><span class="mw-cite-backlink">^ <a href="#cite_ref-MPR=1999-03-08_2-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-MPR=1999-03-08_2-1"><sup><i><b>b</b></i></sup></a></span> <span class="reference-text"><cite id="CITEREFDiefendorff,_Keith1999" class="citation journal cs1">Diefendorff, Keith (March 8, 1999). <a rel="nofollow" class="external text" href="http://docencia.ac.upc.edu/ETSETB/SEGPAR/microprocessors/pentium3%20(mpr).pdf">"Pentium III = Pentium II + SSE: Internet SSE Architecture Boosts Multimedia Performance"</a> <span class="cs1-format">(PDF)</span>. <i><a href="Microprocessor_Report" title="Microprocessor Report">Microprocessor Report</a></i>. <b>13</b> (3). <a rel="nofollow" class="external text" href="https://web.archive.org/web/20180417203519/http://docencia.ac.upc.edu/ETSETB/SEGPAR/microprocessors/pentium3%20%28mpr%29.pdf">Archived</a> <span class="cs1-format">(PDF)</span> from the original on April 17, 2018<span class="reference-accessdate">. Retrieved <span class="nowrap">September 1,</span> 2017</span>.</cite></span>

</li>

<li id="cite_note-extman-3"><span class="mw-cite-backlink"><b><a href="#cite_ref-extman_3-0">^</a></b></span> <span class="reference-text"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20080517014932/http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/22466.pdf">"AMD Extensions to the 3DNow and MMX Instruction Sets Manual"</a> <span class="cs1-format">(PDF)</span>. <a href="Advanced_Micro_Devices%2C_Inc." class="mw-redirect" title="Advanced Micro Devices, Inc.">Advanced Micro Devices, Inc.</a> March 2000. Archived from <a rel="nofollow" class="external text" href="https://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/22466.pdf">the original</a> <span class="cs1-format">(PDF)</span> on May 17, 2008<span class="reference-accessdate">. Retrieved <span class="nowrap">April 18,</span> 2024</span>.</cite></span>

</li>

<li id="cite_note-:0-4"><span class="mw-cite-backlink"><b><a href="#cite_ref-:0_4-0">^</a></b></span> <span class="reference-text"><cite id="CITEREFVance2007" class="citation web cs1"><a href="Ashlee_Vance" title="Ashlee Vance">Vance, Ashlee</a> (August 3, 2007). <a rel="nofollow" class="external text" href="https://www.theregister.co.uk/2007/08/30/amd_sse5/">"AMD plots single thread boost with x86 extensions"</a>. <i><a href="The_Register" title="The Register">The Register</a></i>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20110427144442/http://www.theregister.co.uk/2007/08/30/amd_sse5/">Archived</a> from the original on April 27, 2011<span class="reference-accessdate">. Retrieved <span class="nowrap">August 24,</span> 2017</span>.</cite></span>

</li>

<li id="cite_note-5"><span class="mw-cite-backlink"><b><a href="#cite_ref-5">^</a></b></span> <span class="reference-text"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://developer.amd.com/wordpress/media/2012/10/AMD64_128_Bit_SSE5_Instrs.pdf">"AMD64 Technology: 128-Bit SSE5 Instruction Set"</a> <span class="cs1-format">(PDF)</span>. <a href="AMD" title="AMD">AMD</a>. August 2007. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20170825103549/http://developer.amd.com/wordpress/media/2012/10/AMD64_128_Bit_SSE5_Instrs.pdf">Archived</a> <span class="cs1-format">(PDF)</span> from the original on August 25, 2017<span class="reference-accessdate">. Retrieved <span class="nowrap">August 24,</span> 2017</span>.</cite></span>

</li>

<li id="cite_note-6"><span class="mw-cite-backlink"><b><a href="#cite_ref-6">^</a></b></span> <span class="reference-text"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://support.amd.com/TechDocs/43479.pdf">"AMD64 Technology AMD64 Architecture Programmer's Manual Volume 6: 128-Bit and 256-Bit XOP and FMA4 Instructions"</a> <span class="cs1-format">(PDF)</span>. AMD. November 2009. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20170131212831/http://support.amd.com/TechDocs/43479.pdf">Archived</a> <span class="cs1-format">(PDF)</span> from the original on January 31, 2017<span class="reference-accessdate">. Retrieved <span class="nowrap">August 24,</span> 2017</span>.</cite></span>

</li>

<li id="cite_note-7"><span class="mw-cite-backlink"><b><a href="#cite_ref-7">^</a></b></span> <span class="reference-text"><cite id="CITEREFGirkar2013" class="citation web cs1">Girkar, Milind (October 1, 2013). <a rel="nofollow" class="external text" href="https://software.intel.com/en-us/isa-extensions/intel-avx">"Intel® Advanced Vector Extensions (Intel® AVX)"</a>. <a href="Intel" title="Intel">Intel</a>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20170825102628/https://software.intel.com/en-us/isa-extensions/intel-avx">Archived</a> from the original on August 25, 2017<span class="reference-accessdate">. Retrieved <span class="nowrap">August 24,</span> 2017</span>.</cite></span>

</li>

<li id="cite_note-8"><span class="mw-cite-backlink"><b><a href="#cite_ref-8">^</a></b></span> <span class="reference-text"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.intel.com/content/www/us/en/support/processors/000005651.html">"Download the Intel® Processor Identification Utility"</a>. Intel. July 24, 2017. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20170825105030/https://www.intel.com/content/www/us/en/support/processors/000005651.html">Archived</a> from the original on August 25, 2017<span class="reference-accessdate">. Retrieved <span class="nowrap">August 24,</span> 2017</span>.</cite></span>

</li>

</ol></div></div>

<div class="mw-heading mw-heading2"><h2 id="External_links">External links</h2></div>

<ul><li><a rel="nofollow" class="external text" href="https://software.intel.com/sites/landingpage/IntrinsicsGuide/">Intel Intrinsics Guide</a></li></ul>

/* start https://en.wikipedia.org/ */

.mw-parser-output .hlist dl,.mw-parser-output .hlist ol,.mw-parser-output .hlist ul{margin:0;padding:0}.mw-parser-output .hlist dd,.mw-parser-output .hlist dt,.mw-parser-output .hlist li{margin:0;display:inline}.mw-parser-output .hlist.inline,.mw-parser-output .hlist.inline dl,.mw-parser-output .hlist.inline ol,.mw-parser-output .hlist.inline ul,.mw-parser-output .hlist dl dl,.mw-parser-output .hlist dl ol,.mw-parser-output .hlist dl ul,.mw-parser-output .hlist ol dl,.mw-parser-output .hlist ol ol,.mw-parser-output .hlist ol ul,.mw-parser-output .hlist ul dl,.mw-parser-output .hlist ul ol,.mw-parser-output .hlist ul ul{display:inline}.mw-parser-output .hlist .mw-empty-li{display:none}.mw-parser-output .hlist dt::after{content:": "}.mw-parser-output .hlist dd::after,.mw-parser-output .hlist li::after{content:" · ";font-weight:bold}.mw-parser-output .hlist dd:last-child::after,.mw-parser-output .hlist dt:last-child::after,.mw-parser-output .hlist li:last-child::after{content:none}.mw-parser-output .hlist dd dd:first-child::before,.mw-parser-output .hlist dd dt:first-child::before,.mw-parser-output .hlist dd li:first-child::before,.mw-parser-output .hlist dt dd:first-child::before,.mw-parser-output .hlist dt dt:first-child::before,.mw-parser-output .hlist dt li:first-child::before,.mw-parser-output .hlist li dd:first-child::before,.mw-parser-output .hlist li dt:first-child::before,.mw-parser-output .hlist li li:first-child::before{content:" (";font-weight:normal}.mw-parser-output .hlist dd dd:last-child::after,.mw-parser-output .hlist dd dt:last-child::after,.mw-parser-output .hlist dd li:last-child::after,.mw-parser-output .hlist dt dd:last-child::after,.mw-parser-output .hlist dt dt:last-child::after,.mw-parser-output .hlist dt li:last-child::after,.mw-parser-output .hlist li dd:last-child::after,.mw-parser-output .hlist li dt:last-child::after,.mw-parser-output .hlist li li:last-child::after{content:")";font-weight:normal}.mw-parser-output .hlist ol{counter-reset:listitem}.mw-parser-output .hlist ol>li{counter-increment:listitem}.mw-parser-output .hlist ol>li::before{content:" "counter(listitem)"\a0 "}.mw-parser-output .hlist dd ol>li:first-child::before,.mw-parser-output .hlist dt ol>li:first-child::before,.mw-parser-output .hlist li ol>li:first-child::before{content:" ("counter(listitem)"\a0 "}

/* end https://en.wikipedia.org/ */

</style><style data-mw-deduplicate="TemplateStyles:r1236075235">

/* start https://en.wikipedia.org/ */

.mw-parser-output .navbox{box-sizing:border-box;border:1px solid #a2a9b1;width:100%;clear:both;font-size:88%;text-align:center;padding:1px;margin:1em auto 0}.mw-parser-output .navbox .navbox{margin-top:0}.mw-parser-output .navbox+.navbox,.mw-parser-output .navbox+.navbox-styles+.navbox{margin-top:-1px}.mw-parser-output .navbox-inner,.mw-parser-output .navbox-subgroup{width:100%}.mw-parser-output .navbox-group,.mw-parser-output .navbox-title,.mw-parser-output .navbox-abovebelow{padding:0.25em 1em;line-height:1.5em;text-align:center}.mw-parser-output .navbox-group{white-space:nowrap;text-align:right}.mw-parser-output .navbox,.mw-parser-output .navbox-subgroup{background-color:#fdfdfd}.mw-parser-output .navbox-list{line-height:1.5em;border-color:#fdfdfd}.mw-parser-output .navbox-list-with-group{text-align:left;border-left-width:2px;border-left-style:solid}.mw-parser-output tr+tr>.navbox-abovebelow,.mw-parser-output tr+tr>.navbox-group,.mw-parser-output tr+tr>.navbox-image,.mw-parser-output tr+tr>.navbox-list{border-top:2px solid #fdfdfd}.mw-parser-output .navbox-title{background-color:#ccf}.mw-parser-output .navbox-abovebelow,.mw-parser-output .navbox-group,.mw-parser-output .navbox-subgroup .navbox-title{background-color:#ddf}.mw-parser-output .navbox-subgroup .navbox-group,.mw-parser-output .navbox-subgroup .navbox-abovebelow{background-color:#e6e6ff}.mw-parser-output .navbox-even{background-color:#f7f7f7}.mw-parser-output .navbox-odd{background-color:transparent}.mw-parser-output .navbox .hlist td dl,.mw-parser-output .navbox .hlist td ol,.mw-parser-output .navbox .hlist td ul,.mw-parser-output .navbox td.hlist dl,.mw-parser-output .navbox td.hlist ol,.mw-parser-output .navbox td.hlist ul{padding:0.125em 0}.mw-parser-output .navbox .navbar{display:block;font-size:100%}.mw-parser-output .navbox-title .navbar{float:left;text-align:left;margin-right:0.5em}body.skin--responsive .mw-parser-output .navbox-image img{max-width:none!important}@media print{body.ns-0 .mw-parser-output .navbox{display:none!important}}

/* end https://en.wikipedia.org/ */

</style></div><div role="navigation" class="navbox" aria-labelledby="Multimedia_Instruction_set_extensions439" style="padding:3px"><table class="nowraplinks mw-collapsible autocollapse navbox-inner" style="border-spacing:0;background:transparent;color:inherit"><tbody><tr><th scope="col" class="navbox-title" colspan="2"><style data-mw-deduplicate="TemplateStyles:r1239400231">

/* start https://en.wikipedia.org/ */

.mw-parser-output .navbar{display:inline;font-size:88%;font-weight:normal}.mw-parser-output .navbar-collapse{float:left;text-align:left}.mw-parser-output .navbar-boxtext{word-spacing:0}.mw-parser-output .navbar ul{display:inline-block;white-space:nowrap;line-height:inherit}.mw-parser-output .navbar-brackets::before{margin-right:-0.125em;content:"[ "}.mw-parser-output .navbar-brackets::after{margin-left:-0.125em;content:" ]"}.mw-parser-output .navbar li{word-spacing:-0.125em}.mw-parser-output .navbar a>span,.mw-parser-output .navbar a>abbr{text-decoration:inherit}.mw-parser-output .navbar-mini abbr{font-variant:small-caps;border-bottom:none;text-decoration:none;cursor:inherit}.mw-parser-output .navbar-ct-full{font-size:114%;margin:0 7em}.mw-parser-output .navbar-ct-mini{font-size:114%;margin:0 4em}html.skin-theme-clientpref-night .mw-parser-output .navbar li a abbr{color:var(--color-base)!important}@media(prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .navbar li a abbr{color:var(--color-base)!important}}@media print{.mw-parser-output .navbar{display:none!important}}

/* end https://en.wikipedia.org/ */

</style><div id="Multimedia_Instruction_set_extensions439" style="font-size:114%;margin:0 4em">Multimedia <a href="Instruction_set_architecture" title="Instruction set architecture">Instruction set</a> <a href="Processor_supplementary_capability" title="Processor supplementary capability">extensions</a></div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Single_instruction%2C_multiple_data" title="Single instruction, multiple data">SIMD</a> (<a href="Reduced_instruction_set_computer" title="Reduced instruction set computer">RISC</a>)</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="DEC_Alpha" title="DEC Alpha">Alpha</a>

<li><a href="Power_ISA" title="Power ISA">Power ISA</a>

<li><a href="SPARC" title="SPARC">SPARC</a>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Single_instruction%2C_multiple_data" title="Single instruction, multiple data">SIMD</a> (<a href="X86" title="X86">x86</a>)</th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

</div></td></tr><tr><td class="navbox-abovebelow" colspan="2"><div>Suspended extensions' dates are <s>struck through</s>.

This template is the original "Multimedia extensions". See Template:Instruction set extensions and talk page: reorganisation underway</div></td></tr></tbody></table></div>

<div class="navbox-styles"></div><div role="navigation" class="navbox" aria-labelledby="Instruction_set_extensions725" style="padding:3px"><table class="nowraplinks mw-collapsible uncollapsed navbox-inner" style="border-spacing:0;background:transparent;color:inherit"><tbody><tr><th scope="col" class="navbox-title" colspan="2"><div id="Instruction_set_extensions725" style="font-size:114%;margin:0 4em"><a href="Instruction_set_architecture" title="Instruction set architecture">Instruction set</a> <a href="Processor_supplementary_capability" title="Processor supplementary capability">extensions</a></div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Single_instruction%2C_multiple_data" title="Single instruction, multiple data">SIMD</a> (<a href="Reduced_instruction_set_computer" title="Reduced instruction set computer">RISC</a>)</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="DEC_Alpha" title="DEC Alpha">Alpha</a>

<li><a href="Power_ISA" title="Power ISA">Power ISA</a>

<li><a href="SPARC" title="SPARC">SPARC</a>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Bit_manipulation_instructions" title="Bit manipulation instructions">Bit manipulation</a> <br> <a href="Find_first_set" title="Find first set">Find first set</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="X86_Bit_manipulation_instruction_set" title="X86 Bit manipulation instruction set">Intel BMI</a> (ABM: 2007, BMI1: 2012, BMI2: 2013, TBM: 2012)</li>

<li><a href="Intel_ADX" title="Intel ADX">Intel ADX</a> (2014)</li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Instruction_set_architecture#Code_density" title="Instruction set architecture">Compressed<br> instructions</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="ARM_architecture_family#Thumb" title="ARM architecture family">Thumb</a></li>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Security and <br> <a href="Cryptographic_accelerator" title="Cryptographic accelerator">cryptography</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="VIA_PadLock" title="VIA PadLock">PadLock</a> (2003)</li>

<li><a href="AES_instruction_set" title="AES instruction set">AES-NI</a> (2008); ARMv8 also has AES instructions</li>

<li><a href="CLMUL_instruction_set" title="CLMUL instruction set">CLMUL</a> (2010)</li>

<li><a href="RDRAND" title="RDRAND">RDRAND</a> (2012)</li>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Transactional_memory" title="Transactional memory">Transactional <br> memory</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Hardware-assisted_virtualization" class="mw-redirect" title="Hardware-assisted virtualization">Virtualization</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

</div></td></tr><tr><td class="navbox-abovebelow" colspan="2"><div>Suspended extensions' dates are <s>struck through</s>.

This template was originally Template:Multimedia extensions. A rename has been effected and recategorisation underway.</div></td></tr></tbody></table></div>

</p></div><div><div class="zim-footer">

This article is issued from <a class="external text" title="Last edited on 2025-06-09" href="https://en.wikipedia.org/wiki/?title=Streaming_SIMD_Extensions&oldid=1294763649">Wikipedia</a>. The text is available under <a class="external text" href="https://creativecommons.org/licenses/by-sa/4.0/deed.en">Creative Commons Attribution-Share Alike 4.0</a> unless otherwise noted. Additional terms may apply for the media files.

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